A FinFET is a field effect transistor including a narrow, active area of a semiconductor material protruding from a substrate so as to resemble a fin. The fin includes source and drain regions. Active areas of the fin are separated by shallow trench isolation (STI), such as SiO2. The FinFET also includes a gate region located between the source and the drain regions. The gate region is formed on a top surface and sidewalls of the fin so the gate region wraps around the fin. The portion of the fin extending under the gate between the source region and the drain region is the channel region.
One type of FinFET is fabricated on silicon on insulator (SOI) wafers. One advantage of SOI FinFETs is the low leakage current from source to drain due to an oxide layer below the fin, thus blocking the leakage current. Another type of FinFET is fabricated on conventional bulk silicon wafers. These FinFETs are known as bulk FinFETs. Fabricating FinFETs on conventional bulk Si wafers can be considered advantageous for two reasons: (i) the lower cost of bulk wafers and (ii) the option to co-integrate conventional planar bulk FETs and FinFETs in a same product.
In FinFETs, the source and the drain region are heavily doped. The source and the drain regions may have a first conductivity type (n-type for NMOS and p-type for PMOS). A problem with existing bulk FinFETs is the existence of a leakage path from source to drain through the part of the fin not controlled by the gate, i.e., the portion of the fin below the gate and adjacent to the STI. The leakage from source to drain through the lower part of the fin is known as punch-through leakage. Punch-through leakage causes an undesirable increase of static power consumption.
In order to solve the problem of punch-through leakage in bulk FinFETs, a lower portion of the fin is doped to have a conductivity type opposite the conductivity type of the source and drain regions (p-type for NMOS; n-type for PMOS). The punch-though-stopper (PTS) dopant is implanted in the part of the fin directly below the channel and below the source and drain regions. Conventionally, well/PTS implantation is conducted after fin/STI formation, resulting in Si lattice damage to the fin from ion scattering due to the SiO2 layer encapsulation of the fins.
Therefore, there is a need for further methods of forming finFET devices resulting in reduced fin damage.